1. Field of the Invention
The present invention relates to a phase regulating circuit comprising a phase discriminator, a first frequency divider whose input serves as an input for a slot clock signal and whose output is connected to the first input of the phase discriminator, a regulating and oscillator component whose input is connected to the output of the phase discriminator and whose output serves to emit a regulated clock signal, and a second frequency divider whose input is connected to the output of the regulator and oscillator component and whose output is connected to a second input of the phase discriminator.
2. Description of the Prior Art
A phase-regulating loop of the type set forth above (phase-locked loop) is disclosed in the book "Halbleiter-Schaltungstechnik" by Tietze et al, 6th Edition, published by Springer-Verlag, Berlin, Heidelberg, New York, Tokyo, 1983, pp. 828-829.
The periodical "Telcom Report", Vol. 9, No. 5, 1986, pp. 261-267 has also described digital signal multiplex devices in which, in the demultiplexer arranged in the receiving path, the clock signal of the respective subsidiary channel is required for its restoration. The restoration of the clock signal is normally carried out using a phase regulating circuit (PLL) in combination with a buffer. Here, the demultiplexed subsidiary channel and its slot clock signal are input into the buffer and read with the low-jitter clock signal obtained from the slot clock signal with the assistance of a high-quality phase regulating circuit. The high-quality phase regulating circuits are needed because of the jitter attenuation requirement.
The regulator and oscillator component generally contains an analog integrator in order to achieve the smallest possible phase deviations. However, an undesired increase in jitter can occur due to the lower cut-off frequency of the integrator.
In a digital signal multiplex device DSMX 2/34, for the restoration of clock signals from sixteen 2-Mbit/s channels an equal number of phase regulating circuits are required.